FabGL
ESP32 Display Controller and Graphics Library
VIA6522.h
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1 /*
2  Created by Fabrizio Di Vittorio (fdivitto2013@gmail.com) - <http://www.fabgl.com>
3  Copyright (c) 2019-2021 Fabrizio Di Vittorio.
4  All rights reserved.
5 
6 
7 * Please contact fdivitto2013@gmail.com if you need a commercial license.
8 
9 
10 * This library and related software is available under GPL v3.
11 
12  FabGL is free software: you can redistribute it and/or modify
13  it under the terms of the GNU General Public License as published by
14  the Free Software Foundation, either version 3 of the License, or
15  (at your option) any later version.
16 
17  FabGL is distributed in the hope that it will be useful,
18  but WITHOUT ANY WARRANTY; without even the implied warranty of
19  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  GNU General Public License for more details.
21 
22  You should have received a copy of the GNU General Public License
23  along with FabGL. If not, see <http://www.gnu.org/licenses/>.
24  */
25 
26 
27 #pragma once
28 
29 
38 #include <stdlib.h>
39 #include <stdint.h>
40 
41 #include "fabgl.h"
42 
43 
44 #define DEBUG6522 0
45 
46 
47 namespace fabgl {
48 
49 
51 // VIA (6522 - Versatile Interface Adapter)
52 
53 
54 // VIA registers
55 #define VIA_REG_ORB_IRB 0x0
56 #define VIA_REG_ORA_IRA 0x1
57 #define VIA_REG_DDRB 0x2
58 #define VIA_REG_DDRA 0x3
59 #define VIA_REG_T1_C_LO 0x4
60 #define VIA_REG_T1_C_HI 0x5
61 #define VIA_REG_T1_L_LO 0x6
62 #define VIA_REG_T1_L_HI 0x7
63 #define VIA_REG_T2_C_LO 0x8
64 #define VIA_REG_T2_C_HI 0x9
65 #define VIA_REG_SR 0xa
66 #define VIA_REG_ACR 0xb // Auxiliary Control Register
67 #define VIA_REG_PCR 0xc // Peripherical Control Register
68 #define VIA_REG_IFR 0xd // Interrupt Flag Register
69 #define VIA_REG_IER 0xe // Interrupt Enable Register
70 #define VIA_REG_ORA_IRA_NH 0xf
71 
72 // IER: VIA interrupt enable/disable bit mask
73 #define VIA_IER_CA2 0x01
74 #define VIA_IER_CA1 0x02
75 #define VIA_IER_SR 0x04
76 #define VIA_IER_CB2 0x08
77 #define VIA_IER_CB1 0x10
78 #define VIA_IER_T2 0x20
79 #define VIA_IER_T1 0x40
80 #define VIA_IER_CTRL 0x80 // 0 = Logic 1 in bits 0-6 disables the corresponding interrupt, 1 = Logic 1 in bits 0-6 enables the corresponding interrupt
81 
82 // VIA, ACR flags
83 #define VIA_ACR_T2_COUNTPULSES 0x20
84 #define VIA_ACR_T1_FREERUN 0x40
85 #define VIA_ACR_T1_OUTENABLE 0x80
86 
87 
91 enum class VIA6522Port {
92  PA,
93  PB,
94  CA1,
95  CA2,
96  CB1,
97  CB2,
98 };
99 
100 
101 #if DEBUG6522
102 static const char * VIAREG2STR[] = { "ORB_IRB", "ORA_IRA", "DDRB", "DDRA", "T1_C_LO", "T1_C_HI", "T1_L_LO", "T1_L_HI", "T2_C_LO", "T2_C_HI", "SR", "ACR", "PCR", "IFR", "IER", "ORA_IRA_NH" };
103 #endif
104 
105 
109 class VIA6522 {
110 public:
111 
112  // callbacks
113  typedef void (*PortOutputCallback)(void * context, VIA6522 * via, VIA6522Port port);
114  typedef void (*PortInputCallback)(void * context, VIA6522 * via, VIA6522Port port);
115 
116  VIA6522(int tag);
117 
118  void setCallbacks(void * context, PortInputCallback portIn, PortOutputCallback portOut) {
119  m_context = context;
120  m_portIn = portIn;
121  m_portOut = portOut;
122  }
123 
124  void reset();
125 
126  void writeReg(int reg, int value);
127  int readReg(int reg);
128 
129  bool tick(int cycles);
130 
131  // set/get "external" state of PA
132  uint8_t PA() { return m_PA; }
133  void setPA(int value);
134  void setBitPA(int bit, bool value);
135  void openBitPA(int bit);
136 
137  // set/get "external" state of PB
138  uint8_t PB() { return m_PB; }
139  void setPB(int value);
140  void setBitPB(int bit, bool value);
141  void openBitPB(int bit);
142 
143  uint8_t CA1() { return m_CA1; }
144  void setCA1(int value) { m_CA1_prev = m_CA1; m_CA1 = value; }
145 
146  uint8_t CA2() { return m_CA2; }
147  void setCA2(int value) { m_CA2_prev = m_CA2; m_CA2 = value; }
148 
149  uint8_t CB1() { return m_CB1; }
150  void setCB1(int value) { m_CB1_prev = m_CB1; m_CB1 = value; }
151 
152  uint8_t CB2() { return m_CB2; }
153  void setCB2(int value) { m_CB2_prev = m_CB2; m_CB2 = value; }
154 
155  uint8_t DDRA() { return m_DDRA; }
156 
157  uint8_t DDRB() { return m_DDRB; }
158 
159  uint8_t tag() { return m_tag; }
160 
161 
162 private:
163 
164  uint8_t m_tag;
165 
166  // timers
167  int m_timer1Counter;
168  uint16_t m_timer1Latch;
169  int m_timer2Counter;
170  uint8_t m_timer2Latch; // timer 2 latch is 8 bits
171  bool m_timer1Triggered;
172  bool m_timer2Triggered;
173 
174  // CA1, CA2
175  uint8_t m_CA1;
176  uint8_t m_CA1_prev;
177  uint8_t m_CA2;
178  uint8_t m_CA2_prev;
179 
180  // CB1, CB2
181  uint8_t m_CB1;
182  uint8_t m_CB1_prev;
183  uint8_t m_CB2;
184  uint8_t m_CB2_prev;
185 
186  // PA, PB
187  uint8_t m_DDRA;
188  uint8_t m_DDRB;
189  uint8_t m_PA; // what actually there is out of 6522 port A
190  uint8_t m_PB; // what actually there is out of 6522 port B
191  uint8_t m_IRA; // input register A
192  uint8_t m_IRB; // input register B
193  uint8_t m_ORA; // output register A
194  uint8_t m_ORB; // output register B
195 
196  uint8_t m_IFR;
197  uint8_t m_IER;
198  uint8_t m_ACR;
199  uint8_t m_PCR;
200  uint8_t m_SR;
201 
202  // callbacks
203  void * m_context;
204  PortInputCallback m_portIn; // input callback
205  PortOutputCallback m_portOut; // output callback
206 
207  #if DEBUG6522
208  int m_tick;
209  #endif
210 };
211 
212 
213 }; // namespace fabgl
Definition: canvas.cpp:36
This file is the all in one include file. Application can just include this file to use FabGL library...
VIA6522Port
I/O port.
Definition: VIA6522.h:91
VIA 6522 emulator.
Definition: VIA6522.h:109